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ltm4620a 1 4620af for more information www.linear.com/4620a typical a pplica t ion descrip t ion dual 13a or single 26a dc/dc module regulator the lt m ? 4620 a is a complete dual 13 a , or single 26 a output switching mode dc/ dc power supply with wider v out range and higher efficiency than the ltm4620. included in the package are the switching controller, power fets, inductors and all supporting components. operating from an input voltage range of 4.5 v to 16v , the ltm4620 a supports two outputs each with an output voltage range of 0.6 v to 5.3 v, set by a single external resistor. its high efficiency design delivers up to 13 a continuous current for each output. only a few input and output capacitors are needed. the device supports frequency synchronization, multiphase operation, burst mode ? operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. fault protection features include overvoltage and over- current protection. the power module is offered in a proprietary space saving and thermally enhanced 15mm 15mm 4.41 mm lga package. the ltm4620a is rohs compliant. 26a, 5v output dc/dc module ? regulator fea t ures a pplica t ions n dual 13a or single 26a output n wide input voltage range: 4.5v to 16v n output voltage range: 0.6v to 5.3v n 1.5% maximum total dc output error n multiphase current sharing with multiple ltm4620as up to 100a n higher efficiency and wider v out range than ltm4620 n differential remote sense amplifier n current mode control/fast transient response n adjustable switching frequency n overcurrent foldback protection n frequency synchronization n internal temperature sensing diode output n output overvoltage protection n pin compatible with the LTM4628 (dual 8a) and ltm4620 (dual 13a) n 15mm 15mm 4.41mm lga package n telecom and networking equipment n industrial equipment 5v efficiency vs i out total output current (a) 1 80 efficiency (%) 85 90 95 100 3 5 8 10 4620a ta01b 12 14 19 2116 23 8v to 5v eff (650khz) 12v to 5v eff (750khz) 4620a ta01a ltm4620a v in temp run1 run2 track1 track2 f set 8.25k 5k 100f 6.3v 2 100f 6.3v 2 phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 v out 5v 26a sw2 pgood2 pgood mode_pllin clkout intv cc extv cc pgood1 pgood sgnd gnd diffp diffn diffout 10k* 5.1v* 120k 0.1f 22f 25v 4 4.7f intv cc 220pf intv cc v out * pull-up resistor and zener are optional v in 7v to 16v intv cc l, lt , lt c , lt m , linear technology, the linear logo, module, burst mode and polyphase are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltm4620a 2 4620af for more information www.linear.com/4620a p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ( note 8) ................................................. C 0.3 v to 18 v v sw 1 , v sw 2 .................................................... C1 v to 18 v pgood 1, pgood2, run 1, run 2, intv cc , extv cc .......................................... C 0.3 v to 6v mode _ pllin , f set , track 1, track 2, diffout , phasmd ............................... C 0. 3 v to intv cc v out 1 , v out 2 , v outs 1 , v outs 2 ..................... C 0.3 v to 6v diffp , diffn ......................................... C 0.3 v to intv cc comp 1, comp 2, v fb 1 , v fb 2 ( note 6) ........ C 0. 3 v to 2.7 v intv cc peak output current ................................ 10 0 ma internal operating temperature range ( note 2) ............................................. C 4 0 c to 125 c storage temperature range .................. C 5 5 c to 125 c peak package body temperature ( mount on top side of pcb only ) ......................... 24 5 c (note 1) lga package 144-lead (15mm 15mm 4.41mm) top view temp clkout sw1 phasmd extv cc 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a sw2 pgood1 pgood2 run2 track2 intv cc v outs2 diffp diffout diffn run1 track1 mode_pllin v fb1 v outs1 f set sgnd comp1 comp2 sgnd v fb2 v in v out2 gnd gnd v out1 sgnd gnd t jmax = 125c, ja = 7c/w, jcbottom = 1.5c/w, jctop = 3.7c/w, jb + jba ? 7c/w, weight = 3.037g values defined per jesd 51-12 lead free finish tray part marking* package description temperature range ltm4620aev#pbf ltm4620aev#pbf ltm4620 av 144-lead (15mm 15mm 4.41mm) lga C40c to 125c ltm4620aiv#pbf ltm4620aiv#pbf ltm4620 av 144-lead (15mm 15mm 4.41mm) lga C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ o r d er i n f or m a t ion symbol parameter conditions min typ max units v in input dc voltage l 4.5 16 v v out output voltage (note 8) l 0.6 5.3 v v out1(dc) , v out2(dc) output voltage, total variation with line and load c in = 22f 3, c out = 100f 1 ceramic, 220f poscap l 1.477 1.5 1.523 v input specifications v run1 , v run2 run pin on/off threshold run rising 1.1 1.25 1.40 v v run1hys , v run2hys run pin on hysteresis 150 mv i inrush(vin) input inrush current at start-up i out = 0a, c in = 22f 3, c ss = 0.01f, c out = 100f 3, v out1 = 1.5v, v out2 = 1.5v, v in = 12v 1 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 26.
ltm4620a 3 4620af for more information www.linear.com/4620a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and v run1 , v run2 at 5v unless otherwise noted. per the typical application in figure 26. symbol parameter conditions min typ max units i q(vin) input supply bias current v in = 12v, v out = 1.5v, burst mode operation v in = 12v, v out = 1.5v, pulse-skipping mode v in = 12v, v out = 1.5v, switching continuous shutdown, run = 0, v in = 12v 5 15 65 50 ma ma ma a i s(vin) input supply current v in = 5v, v out = 1.5v, i out = 13a v in = 12v, v out = 1.5v, i out = 13a 4.6 1.853 a a output specifications i out1(dc) , i out2(dc) output continuous current range v in = 12v, v out = 1.5v (notes 7, 8) 0 13 a v out1(line) /v out1 v out2(line) /v out2 line regulation accuracy v out = 1.5v, v in from 4.75v to 16v i out = 0a for each output, l 0.01 0.025 %/v v out1 /v out1 v out2 /v out2 load regulation accuracy for each output, v out = 1.5v, 0a to 13a v in = 12v (note 7) l 0.35 0.5 % v out1(ac) , v out2(ac) output ripple voltage for each output, i out = 0a, c out = 100f 3/ x7r/ceramic, 470f poscap, v in = 12v, v out = 1.5v, frequency = 400khz 15 mv p-p f s (each channel) output ripple voltage frequency v in = 12v, v out = 1.5v, f set = 1.25v (note 4) 500 khz f sync (each channel) sync capture range 400 780 khz v outstart (each channel) turn-on overshoot c out = 100f/x5r/ceramic, 470f poscap, v out = 1.5v, i out = 0a v in = 12v 10 10 mv mv t start (each channel) turn-on time c out = 100f/x5r/ceramic, 470f poscap, no load, track/ss with 0.01f to gnd, v in = 12v 5 5 ms ms v out(ls) (each channel) peak deviation for dynamic load load: 0% to 50% to 0% of full load c out = 22f 3/x5r/ceramic, 470f poscap v in = 12v, v out = 1.5v 30 mv t settle (each channel) settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 12v, c out = 100f, 470f poscap 20 s i out(pk) (each channel) output current limit v in = 12v, v out = 1.5v 20 a control section v fb1 , v fb2 voltage at v fb pins i out = 0a, v out = 1.5v l 0.592 0.600 0.606 v i fb (note 6) C5 C20 na v ovl feedback overvoltage lockout l 0.64 0.66 0.68 v track1 (i), track2 (i) track pin soft-start pull-up current track1 (i),track2 (i) start at 0v 1 1.25 1.5 a uvlo undervoltage lockout v in falling v in rising 3.3 3.9 v v uvlo hysteresis 0.6 v t on(min) minimum on-time (note 6) 90 ns r fbhi1 , r fbhi2 resistor between v outs1 , v outs2 and v fb1 , v fb2 pins for each output 59.90 60.4 60.75 k? v pgood1 , v pgood2 low pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 5 a v pgood pgood trip level v fb with respect to set output voltage v fb ramping negative v fb ramping positive C10 10 % %
ltm4620a 4 4620af for more information www.linear.com/4620a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range. specified as each individual output channel. t a = 25c (note 2), v in = 12v and vrun1, vrun2 at 5v unless otherwise noted. per the typical application in figure 26. symbol parameter conditions min typ max units intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 16v 4.8 5 5.2 v v intvcc load regulation intv cc load regulation i cc = 0ma to 50ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v extvcc(drop) extv cc dropout i cc = 20ma, v extvcc = 5v 50 100 mv v extvcc(hyst) extv cc hysteresis 200 mv oscillator and phase-locked loop frequency nominal nominal frequency f set = 1.2v 450 500 550 khz frequency low lowest frequency f set = 0v (note 5) 210 250 290 khz frequency high highest frequency f set > 2.4v, up to intv cc 700 780 860 khz f set frequency set current 9 10 11 a r mode_pllin mode_pllin input resistance 250 k clkout phase (relative to v out1 ) phasmd = gnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg clk high clk low clock high output voltage clock low output voltage 2 0.2 v v differential amplifier a v differential amplifier gain 1 v r in input resistance measured at diffp input 80 k? v os input offset voltage v diffp = v diffout = 1.5v, i diffout = 100a 3 mv psrr differential amplifier power supply rejection ratio 5v < v in < 16v 90 db i cl maximum output current 2 ma v out(max) maximum output voltage i diffout = 300a intv cc C 1.4 v gbw gain bandwidth product 3 mhz v temp diode connected pnp i = 100a 0.6 v tc temperature coefficient l 2.2 mv/c note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4620a is tested under pulsed load conditions such that t j t a . the ltm4620ae is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4620ai is guaranteed over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: tw o outputs are tested separately and the same testing condition is applied to each output. note 4: the switching frequency is programmable from 400khz to 750khz. note 5: the ltm4620a is designed to operate from 400khz to 750khz note 6: these parameters are tested at wafer sort. note 7: see output current derating curves for different v in , v out and t a . note 8: output current limitations. for 10v v in 16v, the 5v output current needs to be limited to 12a/channel, switching frequency = 750khz. derating cur ves apply. for 7v v in 9v, the 5v output current needs to be limited to 13a/channel, switching frequency = 750khz. derating curves apply. all other input and output combinations are 13a/channel with recommended switching frequency included in the efficiency graphs. derating curves apply.
ltm4620a 5 4620af for more information www.linear.com/4620a typical p er f or m ance c harac t eris t ics 12v to 1v load step response 12v to 1.8v load step response 12v to 1.2v load step response 12v to 2.5v load step response 12v to 1.5v load step response 12v to 3.3v load step response efficiency vs output current, v in = 8v efficiency vs output current, v in = 12v efficiency vs output current, v in = 5v output current (a) 1 70 efficiency (%) 75 80 85 90 100 2.4 3.8 5.2 6.6 8.0 9.4 4620a g01 10.8 12.2 95 5v to 1v (400khz) 5v to 1.2v (400khz) 5v to 1.5v (400khz) 5v to 1.8v (500khz) 5v to 2.5v (500khz) 5v to 3.3v (500khz) 20mv/div 50s/div c ff = 150pf c out = 2 470f 9m each poscap 1 100f ceramic 4620a g04 5a/div 6a/s step 20mv/div 50s/div c ff = 150pf c out = 2 470f 9m each poscap 1 100f ceramic 4620a g05 5a/div 6a/s step 50mv/div 50s/div c ff = 47pf c out = 220f 9m poscap 100f ceramic 4620a g06 5a/div 6a/s step 50mv/div 50s/div c ff = 33pf c out = 220f 9m poscap 100f ceramic 4620a g07 5a/div 6a/s step 50mv/div 50s/div c ff = 100pf c out = 220f 9m poscap 100f ceramic 4620a g08 5a/div 6a/s step 100mv/div 50s/div c ff = 33pf c out = 100f 15m poscap 100f ceramic 4620a g09 5a/div 6a/s step output current (a) 1 70 efficiency (%) 75 80 85 90 100 2.4 3.8 5.2 6.6 8.0 9.4 4620a g02 10.8 12.2 95 8v to 1v (400khz) 8v to 1.2v (400khz) 8v to 1.5v (500khz) 8v to 1.8v (600khz) 8v to 2.5v (650khz) 8v to 3.3v (700khz) 8v to 5v (750khz) tie 5v out to extv cc output current (a) 1 70 efficiency (%) 75 80 85 90 100 2.4 3.8 5.2 6.6 8.0 9.4 4620a g03 10.8 12.2 95 12v to 1v (400khz) 12v to 1.2v (400khz) 12v to 1.5v (500khz) 12v to 1.8v (600khz) 12v to 2.5v (650khz) 12v to 3.3v (700khz) 12v to 5v (750khz) tie 5v out to extv cc
ltm4620a 6 4620af for more information www.linear.com/4620a typical p er f or m ance c harac t eris t ics 12v to 5v load step response single phase start-up, 13a load output current sharing 12v to 1.5v, 0a load short-circuit testing 12v to 1.5v, 13a no load short-circuit testing 12v to 1.5v start-up, no load 500mv/div 10ms/div 12v in , 1.5v out at no load c out = 2 470f, 4v sanyo poscap, 1 100f, 6.3v ceramic soft-start capacitor = 0.01f use run pin to control start-up 4620a g12 500mv/div 10ms/div 12v in , 1.5v out at 13a load c out = 2 470f, 4v sanyo poscap, 1 100f, 6.3v ceramic soft-start capacitor = 0.01f use run pin to control start-up 4620a g13 500mv/div 1a/div 25ms/div 12v in , 1.5v out at 0a load c out = 2 470f, 4v sanyo poscap, 1 100f, 6.3v x5r ceramic soft-start capacitor = 0.01f use run pin to control start-up 4620a g14 500mv/div 10a/div 25ms/div 12v in , 1.5v out at 13a load c out = 2 470f, 4v sanyo poscap, 1 100f, 6.3v x5r ceramic soft-start capacitor = 0.01f use run pin to control start-up 4620a g15 100mv/div 50s/div c ff = 47pf c out = 100f ceramic x7r 4620a g10 5a/div 6a/s step total output current (a) each channel current (a) 6 9 10 4620a g11 5 4 0 19 22 4 8 16 2 6 11 2 12 11 8 7 3 1 i out1 i out2
ltm4620a 7 4620af for more information www.linear.com/4620a p in func t ions v out1 ( a1-a5, b1-b5, c1-c4): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. review table 5. see note 8 in the electrical characteristics section for output current guideline. gnd ( a6-a7, b6-b7, d1-d4, d9-d12, e1-e4, e10-e12, f1-f3, f10-f12, g1, g3, g10, g12, h1-h7, h9-h12, j1, j5, j8, j12, k1, k5-k8, k12, l1, l12, m 1 , m12): power ground pins for both input and output returns. v out2 ( a8-a12, b8-b12, c9-c12): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance di- rectly between these pins and gnd pins. review table 5. see note 8 in the electrical characteristics section for output current guideline. v outs1 , v outs2 ( c5, c8): this pin is connected to the top of the internal top feedback resistor for each output. the pin can be directly connected to its specific output, or connected to diffout when the remote sense amplifier is used. in paralleling modules, one of the v outs pins is connected to the diffout pin in remote sensing or directly to v out with no remote sensing. it is very important to connect these pins to either the diffout or v out since this is the feedback path, and cannot be left open. see the applications information section. f set (c6): frequency set pin. a 10 a current is sourced from this pin. a resistor from this pin to ground sets a voltage that in turn programs the operating frequency. alternatively, this pin can be driven with a dc voltage that can set the operating frequency. see the applications information section. sgnd ( c7, d6, g6-g7, f6-f7): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd in the ap- plication. see layout guidelines in figure 25. v fb1 , v fb2 ( d5, d7): the negative input of the error amplifier for each channel. internally, this pin is con- nected to v outs1 or v outs2 with a 60.4 k? precision resistor. different output voltages can be programmed with an additional resistor between v fb and gnd pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section for details. track1, track2 ( e5, d8): output voltage tracking pin and soft-start inputs. each channel has a 1.3 a pull-up current source. when one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. the remaining channel can be set up as the slave, and have the masters output applied through a voltage divider to the slave out- puts track pin. this voltage divider is equal to the slave outputs feedback divider for coincidental tracking. see the applications information section. comp1, comp 2 ( e6, e7): current control threshold and error amplifier compensation point for each channel. the current comparator threshold increases with this control voltage. tie the comp pins together for parallel operation. the device is internal compensated. diffp (e8): positive input of the remote sense amplifier. this pin is connected to the remote sense point of the output voltage. diffamp can be used for 3.3 v outputs. see the applications information section. diffn (e9): negative input of the remote sense amplifier. this pin is connected to the remote sense point of the output gnd. diffamp can be used for 3.3 v outputs. see the applications information section. mode_pllin (f4): force continuous mode, burst mode operation, or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels into force continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leaving the pin floating will enable burst mode operation. a clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. (recommended to use test points to monitor signal pin connections.) package row and column labeling m ay vary among module products. review each package layout carefully.
ltm4620a 8 4620af for more information www.linear.com/4620a p in func t ions run1, run 2 ( f5, f9): run control pin. a voltage above 1.25v will turn on each channel in the module. a voltage below 1.25 v on the run pin will turn off the related chan- nel. each run pin has a 1 a pull-up current, once the run pin reaches 1.2 v an additional 4.5 a pull-up current is added to this pin. diffout (f8): internal remote sense amplifier output. connect this pin to v outs1 or v outs2 depending on which output is using remote sense. in parallel operation con- nect one of the v outs pin to diffout for remote sensing. diffamp can be used for 3.3v outputs. sw1, sw 2 ( g2, g11): switching node of each channel that is used for testing purposes. also an r-c snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. see the applications information section. phasmd (g4): connect this pin to sgnd, intv cc , or float- ing this pin to select the phase of clkout to 60 degrees, 120 degrees, and 90 degrees respectively. clkout (g5): clock output with phase control using the phasmd pin to enable multiphase operation between devices. see the applications information section. pgood 1, pgood2 (g 9, g 8): output voltage power good indicator. open drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. intv cc (h8): internal 5 v regulator output. the control circuits and internal gate drivers are powered from this voltage. decouple this pin to pgnd with a 4.7 f low esr tantalum or ceramic. intv cc is activated when either run1 or run2 is activated. temp (j6): onboard temperature diode for monitoring the vbe junction voltage change with temperature. see the applications information section. extv cc (j7): external power input that is enabled through a switch to intv cc whenever extv cc is greater than 4.7 v. do not exceed 6 v on this input, and connect this pin to v in when operating v in on 5 v. an efficiency increase will occur that is a function of the (v in C intv cc ) multiplied by power mosfet driver current. typical current require- ment is 30 ma. v in must be applied before extv cc , and extv cc must be removed before v in . a 5 v output can be tied to this pin to increase efficiency. see applications information section. v in ( m2-m11, l2-l11, j2-j4, j9-j11, k2-k4, k9-k11): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. (recommended to use test points to monitor signal pin connections.)
ltm4620a 9 4620af for more information www.linear.com/4620a s i m pli f ie d b lock diagra m decoupling r equire m en t s symbol parameter conditions min typ max units c in1, c in2 c in3, c in4 external input capacitor requirement (v in1 = 4.75v to 16v, v out1 = 1.5v) (v in2 = 4.75v to 16v, v out2 = 1.2v) i out1 = 13a i out2 = 13a (note 8) 22 22 f f c out1 c out2 external output capacitor requirement (v in1 = 4.75v to 16v, v out1 = 1.5v) (v in2 = 4.75v to 16v, v out2 = 1.2v) i out1 = 13a i out2 = 13a (note 8) 300 300 f f t a = 25c. use figure 1 configuration. figure 1. simplified ltm4620a block diagram 4620a f01 temp clkout run1 mode_pllin phasemd track1 = 100a 4.7f ss cap 1f c in1 22f 25v v in v in c in2 22f 25v r fb2 60.4k mtop1 mbot1 power control 2.2f 0.56h 60.4k c out1 r fb1 40.2k + v out1 1.5v/13a v out2 1.2v/13a v fb1 gnd gnd gnd gnd sw2 sw1 pgood2 pgood1 internal comp internal comp internal filter 1f c in3 22f 25v mtop2 mbot2 c in4 22f 25v 2.2f 0.56h c out2 + + ? 60.4k v out1 v out2 v fb2 v outs2 v outs1 r fset v in r t v in r t ss cap diffout diffn diffp comp1 sgnd track2 intv cc extv cc run2 comp2 f set sgnd
ltm4620a 10 4620af for more information www.linear.com/4620a o pera t ion power module description the ltm4620a is a dual-output standalone nonisolated switching mode dc/dc power supply. it can provide two 13a outputs with few external input and output capacitors and setup components. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5.3v dc over 4.5 v to 16 v input voltages. the typical application schematic is shown in figure 26. see note 8 in the electrical characteristics section for output current guideline. the ltm4620 a has dual integrated constant- frequency cur - rent mode regulators and built-in power mosfet devices with fast switching speed. the typical switching frequency is 500 khz. for switching-noise sensitive applications, it can be externally synchronized from 400 khz to 780khz. a resistor can be used to program a free run frequency on the f set pin. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4620 a module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. internal overvoltage and undervoltage comparators pull the open-drain pgood outputs low if the output feedback voltage exits a 10% window around the regulation point. as the output voltage exceeds 10% above regulation, the bottom mosfet will turn on to clamp the output voltage. the top mosfet will be turned off. this overvoltage protect is feedback voltage referred. pulling the run pins below 1.1 v forces the regulators into a shutdown state, by turning off both mosfets. the track pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. see the applications information section. the ltm4620a is internally compensated to be stable over all operating conditions. table 5 provides a guide line for input and output capacitances for several operating con- ditions. the linear technology module power design tool will be provided for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. a differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in par- allel operation sensing the output voltage at the load point. multiphase operation can be easily employed with the mode_pllin, phasmd, and clkout pins. up to 12 phases can be cascaded to run simultaneously with re- spect to each other by programming the phmode pin to different levels. see the applications information section. high efficiency at light loads can be accomplished with selectable burst mode operation or pulse-skipping opera- tion using the mode pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. see the applications information section for details. a temperature diode is included inside the module to moni- tor the temperature of the module. see the applications information section for details. the switching node pins are available for functional opera- tion monitoring and a resistor-capacitor snubber circuit can be careful placed on the switching node pin to ground to dampen any high frequency ringing on the transition edges. see the applications information section for details .
ltm4620a 11 4620af for more information www.linear.com/4620a the typical ltm4620a application circuit is shown in figure 26. external component selection is primarily determined by the maximum load current and output voltage. refer to table 5 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage. each output of the ltm4620a is capable of 95% duty cycle at 500 khz, but the v in to v out minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. minimum on- time t on( min) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t on(min) < d/f sw , where d is duty cycle and f sw is the switching frequency. t on(min) is specified in the electrical parameters as 90ns. see note 8 in the electrical characteristics section for output current guideline. output voltage programming the pwm controller has an internal 0.6 v reference voltage. as shown in the block diagram , a 60.4 k? internal feedback resistor connects between the v outs1 to v fb1 and v outs2 to v fb2 . it is very important that these pins be connected to their respective outputs for proper feedback regulation. overvoltage can occur if these v outs1 and v outs2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. the output voltage will default to 0.6 v with no feedback resistor on either v fb1 or v fb2 . adding a resistor r fb from v fb pin to gnd programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out 0.6v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5v r fb open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k for parallel operation of multiple channels the same feed- back setting resistor can be used for the parallel design. this is done by connecting the v outs1 to the output as shown in figure 2, thus tying one of the internal 60.4k a pplica t ions i n f or m a t ion resistors to the output . all of the v fb pins tie together with one programming resistor as shown in figure 2. in parallel operation, the v fb pins have an i fb current of 20na maximum each channel. to reduce output voltage error due to this current, an additional v outs pin can be tied to v out , and an additional r fb resistor can be used to lower the total thevenin equivalent resistance seen by this current. for example in figure 2, the total thevenin equivalent resistance of the v fb pin is (60.4 k//r fb ), which is 30.2 k where r fb is equal to 60.4k for a 1.2v output. four phases connected in parallel equates to a worse case feedback current of 4 ? i fb = 80 na maximum. the voltage error is 80na ? 30.2k = 2.4 mv. if v outs2 is connected, as shown in figure 2, to v out , and another 60.4 k resistor is connected from v fb2 to ground, then the voltage error is reduced to 1.2 mv. if the voltage error is acceptable then no additional connec- tions are necessary. the onboard 60.4 k resistor is 0.5% accurate and the v fb resistor can be chosen by the user to be as accurate as needed. all comp pins are tied together for current sharing between the phases. the track pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. the soft-start equation will need to have the soft- start current parameter increased by the number of paralleled channels. see track/soft- start pin section. figure 2. 4-phase parallel configurations 4620a f02 60.4k track1 track2 v out1 v outs1 v fb1 v fb2 comp1 4 paralleled outputs for 1.2v at 50a optional connection comp2 v outs2 v out2 60.4k 60.4k track1 track2 0.1f v out1 v outs1 v fb1 v fb2 comp1 comp2 v outs2 v out2 60.4k ltm4620a ltm4620a r fb 60.4k optional r fb 60.4k use to lower total equivalent resistance to lower i fb voltage error
ltm4620a 12 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion input capacitors the ltm4620a module should be connected to a low ac- impedance dc source. for the regulator input four 22f input ceramic capacitors are used for rms ripple current . a 47 f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance . this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1 ? d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated electrolytic aluminum capacitor, polymer capacitor. output capacitors the ltm4620a is designed for low output voltage ripple noise and good transient response. the bulk output capacitors defined as c out are chosen with low enough effective series resistance ( esr) to meet the output volt- age ripple and transient requirements. c out can be a low esr tantalum capacitor, the low esr polymer capacitor or ceramic capacitor. the typical output capacitance range for each output is from 200 f to 470 f. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7 a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 5 matrix, and the linear technology module power design tool will be provided for stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. the linear technology module power design tool can calculate the output ripple reduc- tion as the number of implemented phases increases by n times. a small value 10 ? to 50 ? resistor can be place in series from v out to the v outs pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. the same resistor could be place in series from v out to diffp and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability.
ltm4620a 13 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion burst mode operation the ltm4620a is capable of burst mode operation on each regulator in which the power mosfets operate in- termittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. burst mode operation is enabled with the mode/pllin pin floating. during this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the comp pin indicates a lower value. the voltage at the comp pin drops when the inductors average current is greater than the load requirement. as the comp voltage drops below 0.5 v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450 a for each output. the load current is now being supplied from the output capacitors. when the output voltage drops, caus- ing comp to rise above 0.5 v, the internal sleep line goes low, and the ltm4620a resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. either regulator can be configured for burst mode operation. pulse-skipping mode operation in applications where low output ripple and high effi- ciency at intermediate currents are desired, pulse - skipping mode should be used. pulse-skipping operation allows the ltm4620a to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode/pllin pin to intv cc enables pulse-skipping operation. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. this mode will maintain higher effective frequencies thus lower output ripple and lower noise than burst mode operation. either regulator can be configured for pulse- skipping mode. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode/pllin pin to gnd. in this mode, induc- tor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continu- ous mode is disabled and inductor current is prevented from reversing until the ltm4620as output voltage is in regulation. either regulator can be configured for force continuous mode. multiphase operation for output loads that demand more than 13 a of current, two outputs in ltm4620a or even multiple ltm4620as can be paralleled to run out of phase to provide more output current without increasing input and output volt- age ripples. the mode/pllin pin allows the ltm4620a to synchronize to an external clock (between 400 khz and 780khz) and the internal phase-locked-loop allows the ltm4620a to lock onto an incoming clock phase as well. the clkout signal can be connected to the mode/pllin pin of the following stage to line up both the frequency and the phase of the entire system. tying the phmode pin to intv cc , sgnd, or ( floating) generates a phase difference ( between mode/pllin and clkout) of 120 degrees, 60 degrees, or 90 degrees respectively. a total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin of each ltm4620a channel to different levels. figure 3 shows a 2- phase design, 4- phase design and a 6-phase design example for clock phasing with the phasmd table. a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater 22
ltm4620a 14 4620af for more information www.linear.com/4620a than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. figure 3. examples of 2-phase, 4-phase, and 6-phase operation with phasmd table 4620a f03 v out2 180 phase 0 phase mode_pllin v out1 phasmd clkout 2-phase design 4-phase design 6-phase design 90 degree float v out2 180 phase 0 phase float mode_pllin v out1 phasmd clkout v out2 270 phase 90 phase float mode_pllin v out1 phasmd clkout 60 degree 60 degree v out2 180 phase 0 phase sgnd mode_pllin v out1 phasmd clkout v out2 240 phase 60 phase sgnd mode_pllin v out1 phasmd clkout v out2 300 phase 120 phase float mode_pllin v out1 phasmd clkout phasmd sgnd controller1 controller2 clkout float intv cc 0 0 0 180 180 240 60 90 120 a pplica t ions i n f or m a t ion the ltm4620a device is an inherently current mode controlled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. figure 26 shows an example of parallel operation and pin connection.
ltm4620a 15 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion figure 4. input rms current ratios to dc load current as a function of duty cycle duty factor (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4620a f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current cancel- lation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure 4 shows this graph. frequency selection and phase-lock loop (mode/pllin and f set pins) the ltm4620a device is operated over a range of frequen- cies to improve power conversion efficiency. it is recom- mended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power mosfet switching losses. higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. the efficiency graphs will show an operating frequency chosen for that condition. select frequency in reference to the highest output voltage.
ltm4620a 16 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion figure 5. operating frequency vs f set pin voltage the ltm4620a switching frequency can be set with an ex- ternal resistor from the f set pin to sgnd. an accurate 10a current source into the resistor will set a voltage that pro- grams the frequency or a dc voltage can be applied. figure 5 shows a graph of frequency setting verses programming voltage. an external clock can be applied to the mode/ pllin pin from 0 v to intv cc over a frequency range of 400khz to 780 khz. the clock input high threshold is 1.6v and the clock input low threshold is 1 v . the ltm4620 a has the pll loop filter components on board. the frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock . both regulators will operate in continuous mode while being externally clock. the output of the pll phase detector has a pair of comple- mentary current sources that charge and discharge the internal filter network. when the external clock is applied then the f set frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. when no external clock is applied, then the internal switch is on, thus connecting the external f set frequency set resistor for free run operation. minimum on-time minimum on-time t on is the smallest time duration that the ltm4620a is capable of turning on the top mosfet on either channel. it is determined by internal timing delays, and the gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple will increase. the on-time can be increased by lowering the switching frequency. a good rule of thumb is to keep on-time longer than 110ns. output voltage tracking output voltage tracking can be programmed externally using the track pins. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to implement coincident tracking. the ltm4620a uses an accurate 60.4 k resistor internally for the top feedback resistor for each channel. figure 6 shows an example of coincident tracking. equations: slave = 1 + 60.4k r ta ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0 v to 0.6 v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage tracking is disabled when v track is more than 0.6 v. r ta in figure 6 will be equal to the r fb for coincident tracking. figure 7 shows the coincident tracking waveforms. f set pin voltage (v) 0 frequency (khz) 900 800 600 400 100 200 700 500 300 0 2 4620a f05 2.5 1 1.5 0.5
ltm4620a 17 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion figure 7. output coincident tracking waveform figure 6. example of output tracking application circuit time master output slave output output voltage 4620a f07 4620a f06 ltm4620a v in temp run1 run2 track1 track2 f set c8 470f 6.3v r fb 60.4k r2 10k c6 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 intv cc sgnd gnd ramp time t softstart = (c ss /1.3a) ? 0.6 * pull-up resistor and zener are optional diffp diffn diffout 40.2k pgood slave v out2 1.2v at 13a v out1 1.5v at 13a c7 470f 6.3v c5 100f 6.3v r4 121k r tb 60.4k r1* 10k d1* 5.1v zener 7v to 16v intermediate bus c ss 0.1f c1 22f 25v r ta 60.4k c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f r9 10k intv cc v in intv cc v out1 1.5v r6 100k pgood master
ltm4620a 18 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion the track pin can be controlled by a capacitor placed on the regulator track pin to ground. a 1.3 a current source will charge the track pin up to the reference voltage and then proceed up to intv cc . after the 0.6v ramp, the track pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the track pins are pulled low when the run pin is below 1.2v. the total soft-start time can be calculated as: t soft-start = c ss 1.3a ? ? ? ? ? ? ? 0.6 regardless of the mode selected by the mode/pllin pin, the regulator channels will always start in pulse-skipping mode up to track = 0.5 v. between track = 0.5 v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once track > 0.54 v. in order to track with another channel once in steady state operation, the ltm4620a is forced into continuous mode operation as soon as v fb is below 0.54 v regardless of the setting on the mode/pllin pin. ratiometric tracking can be achieved by a few simple cal- culations and the slew rate value applied to the masters track pin. as mentioned above, the track pin has a control range from 0 to 0.6 v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 60.4k = r tb where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal the 60.4k. r ta is derived from equation: r ta = 0.6v v fb 60.4k + v fb r fb ? v track r tb where v fb is the feedback voltage reference of the regula- tor, and v track is 0.6 v. since r tb is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 60.4 k, and r ta = 60.4 k in figure 6. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example, mr = 1.5v/1ms, and sr = 1.2v/1ms. then r tb = 76.8k. solve for r ta to equal to 49.9k. each of the track pins will have the 1.3 a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4 k is used then a 6.04 k can be used to reduce the track pin offset to a negligible value. power good the pgood pins are open drain pins that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. stability compensation the module has already been internally compensated for all output voltages. table 5 is provided for most ap- plication requirements. the linear technology module power design tool will be provided for other control loop optimization. run enable the run pins have an enable threshold of 1.4 v maximum, typically 1.25 v with 150 mv of hysteresis. they control the turn on each of the channels and intv cc . these pins can be pulled up to v in for 5 v operation, or a 5 v zener diode can be placed on the pins and a 10 k to 100 k resistor can be placed up to higher than 5v input for enabling the channels. the run pins can also be used for output voltage sequencing. in parallel operation the run pins can be tie together and
ltm4620a 19 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion controlled from a single control. see the typical applica- tion circuits in figure 26. intv cc and extv cc the ltm4620a module has an internal 5 v low dropout regulator that is derived from the input voltage. this regu- lator is used to power the control circuitry and the power mosfet drivers. this regulator can source up to 70ma, and typically uses ~30 ma for powering the device at the maximum frequency. this internal 5 v supply is enabled by either run1 or run2. extv cc allows an external 5 v supply to power the ltm4620a and reduce power dissipation from the internal low dropout 5 v regulator. the power loss savings can be calculated by: ( v in C 5v) ? 30ma = ploss extv cc has a threshold of 4.7 v for activation, and a maxi- mum rating of 6 v. when using a 5 v input, connect this 5v input to extv cc also to maintain a 5 v gate drive level. extv cc must sequence on after v in , and extv cc must sequence off before v in . when designing a 5 v output, connect this 5 v output to extv cc . use an external 5 v bias on extv cc to improve efficiency. differential remote sense amplifier an accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. this is especially true for high current loads. the amplifier can be used on one of the two channels, or on a single parallel output. it is very important that the diffp and diffn are connected properly at the output, and diffout is connected to either v outs1 or v outs2 . in parallel operation, the diffp and diffn are connected properly at the output, and diffout is connected to one of the v outs pins. review the parallel schematics in figure 29 and review figure 2. the diffamp can only be used for output voltage 3.3v. sw pins the sw pins are generally for testing purposes by moni- toring these pins. these pins can also be used to dampen out switch node ringing caused by lc parasitic in the switched current paths. usually a series r-c combina- tion is used called a snubber circuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the power path board inductance in combination with the mosfet interconnect bond wire inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre- quency can be measured for its value. the impedance z can be calculated: z(l) = 2fl, where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z(c ) = 1/(2fc). these values are a good place to start with. modification to these components should be made to attenuate the ringing with the least amount of power loss. temperature monitoring measuring the absolute temperature of a diode is pos- sible due to the relationship between current, voltage and temperature described by the classic diode equation: i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ? ln i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor ( typically close to 1.0) and i s (satura- tion current) is a process dependent parameter. v t can be broken out to: v t = k ? t q
ltm4620a 20 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmanns constant. v t is approximately 26 mv at room temperature (298 k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable temperature sensors. the i s term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d = ? k q where k d = 8.62 ?5 , and knowing ln(i d /i s ) is always posi- tive because i d is always greater than i s , leaves us with the equation that: v d = t(kelvin) ? k d ? ln i d i s where v d appears to increase with temperature. it is com- mon knowledge that a silicon diode biased with a current source has an approximately C2 mv/c temperature rela- tionship (figure 8), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln (i d /i s ) absolute value yielding an approximately C2mv/c composite diode voltage slope. figure 8. diode voltage v d vs temperature t(c) for different bias currents to obtain a linear voltage proportional to temperature we cancel the i s variable in the natural logarithm term to remove the i s dependency from the following equation. this is accomplished by measuring the diode voltage at two currents i 1 , and i 2 , where i 1 = 10???i 2 ), subtracting we get: v d = t(kelvin) ? k d ? ln i 1 i s ? t(kelvin) ? k d ? ln i 2 i s combining like terms, then simplifying the natural log terms yields: v d = t(kelvin) ? k d ? ln(10) and redefining constant k' d = k d ? in(10) = 198v/k yields v d = k' d ? t(kelvin) solving for temperature: t(kelvin) = v d k' d , t(kelvin) = [ c] + 273.15, [ c] = t(kelvin) ? 273.15 means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198 v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected pnp transistor can be pulled up to v in with a resistor to set the current to 100 a for using this diode connected transistor as a general temperature monitor by monitoring the diode voltage drop with tem- perature, or a specific temperature monitor can be used that injects two currents that are at a 10:1 ratio for very accurate temperature monitoring. see figure 24 for an example. 4620a f08 temperature (c) ?173 ?73 27 127 diode voltage (v) 0.4 0.6 0.8 1.0 ?v d i d = 100a i d = 10a
ltm4620a 21 4620af for more information www.linear.com/4620a thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param- eters defined by jesd51-9 and are intended for use with finite element analysis ( fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a module package mounted to a hardware test board also defined by jesd 51-9 ( test boards for area array surface mount package thermal measurements). the motivation for providing these thermal coefficients in found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulators thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal per formance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef- ficients are quoted or paraphrased below: a pplica t ions i n f or m a t ion 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. this environment is sometimes referred to as still air although natural convection causes the air to move . this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. in the typical module, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part . as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. figure 9. graphical representation of jesd51-12 thermal coefficients 4620a f10 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance (jesd 51-9 defined board) case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance
ltm4620a 22 4620af for more information www.linear.com/4620a 4. jb , the thermal resistance from junction to the printed circuit board, is the junction- to- board thermal resistance where almost all of the heat flows through the bottom of the module and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a por- tion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd 51-9. a graphical representation of the aforementioned ther- mal resistances is given in figure 9; blue resistances are contained within the module regulator, whereas green resistances are external to the module. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module. for example, in normal board-mounted applications, never does 100% of the devices total power loss ( heat) thermally conduct exclu- sively through the top or exclusively through bottom of the module as the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within a sip ( system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the module and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software-defined jedec environment consistent with jsed51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec- defined thermal resistance values; (3) the model and fea software is used to evaluate the module with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled- environment chamber while operating the device at the same power loss as that which was simulated. an outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. after these laboratory test have been performed and correlated to the module model, then the jb and ba are summed together to cor- relate quite well with the module model with no airflow or heat sinking in a properly define chamber. this jb + ba value is shown in the pin configuration section and should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. a pplica t ions i n f or m a t ion
ltm4620a 23 4620af for more information www.linear.com/4620a the ltm4620a module has been designed to effectively remove heat from both the top and bottom of the pack- age. the bottom substrate material has very low thermal resistance to the printed circuit board and the exposed top metal is thermally connected to the power devices and the power inductors. an external heat sink can be applied to the top of the device for excellent heat sinking with airflow. basically all power dissipating devices are mounted directly to the substrate and the top exposed metal. this provides two low thermal resistance paths to remove heat. figure 10 shows a temperature plot of the ltm4620a with bga heat sink and 200 lfm airflow with ~5.3 w of internal dissipation. figure 11 shows a temperature plot of the ltm4620a with no heat sink and 200 lfm airflow with ~6.5 w of internal dissipation. these plots equate to a paralleled 1.2 v at 26 a design, and a 5v at 25a design operating from a 12v input. safety considerations the ltm4620a modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input voltage will source very large currents to ground through the failed internal top mosfet and enabled internal bot- tom mosfet. this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the device does support over current protection. a tempera- ture diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the run pin. figure 10. ltm4620a 12v to 1.2v at 26a with 200lfm air flow figure 11. ltm4620a 12v to 5v at 25a with 200lfm air flow a pplica t ions i n f or m a t ion
ltm4620a 24 4620af for more information www.linear.com/4620a power derating the 1v, 2.5 v and 5 v power loss curves in figures 12 to 14 can be used in coordination with the load current derating curves in figures 15 to 24 for calculating an approximate ja thermal resistance for the ltm4620 a with various heat sinking and airflow conditions. the power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125 c. these factors come from the fact that the power loss of the regulator increases about 45% from 25 c to 150 c, thus a 45% spread over 125c delta equates to ~0.35%/ c loss increase. a 125c maximum junction minus 25 c room temperature equates to a 100 c increase. this 100 c increase multiplied by 0.35%/c equals a 35% power loss increase at the 125c junction, thus the 1.35 multiplier. the derating curves are plotted with ch1 and ch2 in parallel single output operation starting at 26 a of load with low ambient temperature. the output voltages are 1v, 2.5 v and 5 v. these are chosen to include the lower and higher output voltage ranges for correlating the ther- mal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis . the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at ~120 c maximum while lowering output current or power while increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure 15, the load current is derated to ~19 a at ~80 c with no air or heat sink and the power loss for the 12 v to 1.0v at 19 a output is a ~5.1 w loss. the 5.1 w loss is calculated with the ~3.75 w room temperature loss from the 12 v to 1.0v power loss curve at 19 a, and the 1.35 multiplying factor at 125 c ambient. if the 80 c ambient temperature is subtracted from the 120 c junction temperature, then the difference of 40 c divided 5.1 w equals a 7.8c/w ja thermal resistance. table 2 specifies a 6.5 to 7 c/w value which is pretty close. the airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. as an example in figure 16, the load current is derated to ~22 a at ~90 c with 200lfm of airflow and the power loss for the 12 v to 1.0 v at 22a output is a ~5.94w loss. the 5.94 w loss is calculated with the ~4.4 w room tem- perature loss from the 12 v to 1.0 v power loss curve at 22a, and the 1.35 multiplying factor at 125 c ambient. if the 90 c ambient temperature is subtracted from the 120c junction temperature, then the difference of 30 c divided 5.94w equals a 5.1 c/w ja thermal resistance. table 2 specifies a 5.5 c/w value which is pretty close. tables 2-4 provide equivalent thermal resistances for 1.0v, 2.5 v and 5v outputs with and without airflow and heat sinking. the derived thermal resistances in tables 2-4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. the printed circuit board is a 1.6 mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 101 mm 114mm. the bga heat sinks are listed below table 4. a pplica t ions i n f or m a t ion
ltm4620a 25 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion table 2. 1.0v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 15, 16 5, 12 figure 12 0 none 6.5 to 7 figures 15, 16 5, 12 figure 12 200 none 5.5 figures 15, 16 5, 12 figure 12 400 none 5 figures 17, 18 5, 12 figure 12 0 bga heat sink 6.5 figures 17, 18 5, 12 figure 12 200 bga heat sink 5 figures 17, 18 5, 12 figure 12 400 bga heat sink 4 table 3. 2.5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 19, 20 5, 12 figure 13 0 none 6.5 to 7 figures 19, 20 5, 12 figure 13 200 none 5.5 to 6 figures 19, 20 5, 12 figure 13 400 none 4.5 figures 21, 22 5, 12 figure 13 0 bga heat sink 6.5 to 7 figures 21, 22 5, 12 figure 13 200 bga heat sink 4 figures 21, 22 5, 12 figure 13 400 bga heat sink 3.5 table 4. 5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figure 23 12 figure 14 0 none 6.5 to 7 figure 23 12 figure 14 200 none 5.5 to 6 figure 23 12 figure 14 400 none 4.5 figure 24 12 figure 14 0 bga heat sink 6.5 to 7 figure 24 12 figure 14 200 bga heat sink 4 figure 24 12 figure 14 400 bga heat sink 3.5 connect 5v output to extv cc to increase efficiency. heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com cool innovations 4-050503p 4-050508p www.coolinnovations.com
ltm4620a 26 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion table 5. output voltage response vs component matrix (refer to figure 23) 0a to 7a load step typical measured values vendors value part number esr tdk, c out1 ceramic 100f 6.3v c4532x5r0j107mz ~1m murata, c out1 ceramic 100f 6.3v grm32er60j107m ~1m avx , c out1 ceramic 100f 6.3v 18126d107 mat ~1m sanyo poscap, c out2 bulk 470f 2r5 2r5tpd470m5 9m sanyo poscap, c out2 bulk 470f 6.3v 6tpd470m 9m sanyo, c in bulk 56f 25v 25svp56m sanyo, poscap c out2 bulk 100f 6.3v 67pe100mi 15m to 18m sanyo, poscap c out2 bulk 220f 2.5v 2r5tpe220m9 sanyo, poscap c out2 bulk 220f 6v 6tpf220ml v out (v) c in (ceramic) c in (bulk)** c out1 (ceramic) c out2 (bulk) c ff (pf) c bot (pf) c comp (pf) v in (v) droop (mv) p-p deviation at 6a load step (mv) recovery time (s) load step (a/s) r fb (k) freq 1 22f 3 56f 100f 470f 2 none none none 5 24 46 30 6 90.9 400 1 22f 3 56f 100f 470f 2 150 none none 12 24 46 30 6 90.9 400 1 22f 3 56f 100f 3 470f 100 none none 12 33 63 23 6 90.9 400 1.2 22f 3 56f 100f 3 470f 100 none none 12 35 70 23 6 60.4 500 1.2 22f 3 56f 100f 470f 2 150 5 24 46 25 6 60.4 500 1.2 22f 3 56f 100f 470f 2 150 12 24 46 25 6 60.4 500 1.5 22f 3 56f 100f 470f 2 220 none 5 26 52 40 6 40.2 550 1.5 22f 3 56f 100f 470f 2 220 12 26 52 40 6 40.2 550 1.5 22f 3 56f 100f 220f 47 12 64 120 20 6 40.2 500 1.8 22f 3 56f 100f 220f 33 12 61 120 20 6 30.2 600 1.8 22f 3 56f 100f 220f 33 5 61 120 20 6 30.2 600 1.8 22f 3 56f 100f 3 none 100 12 80 160 18 6 30.2 600 2.5 22f 3 56f 100f 3 none 150 none 47 12 60 120 20 6 19.1 650 2.5 22f 3 56 f 100f 3 none 150 none 47 12 60 120 20 6 19.1 650 3.3 22f 3 56f 100f 100f 33 12 118 240 30 6 13.3 700 3.3 22f 3 56f 100f 2 100 12 120 240 20 6 13.3 700 5 22f 3 56f 100f 47 12 188 382 25 6 8.25 750 5 22f 3 56f 100f 12 180 360 20 6 8.25 750 **bulk capacitance is optional if v in has very low input impedance.
ltm4620a 27 4620af for more information www.linear.com/4620a figure 12. 2.5v power loss curve figure 13. 1v power loss curve figure 15. 12v to 1v derating curve, no heat sink figure 16. 5v to 1v derating curve, no heat sink figure 17. 12v to 1v derating curve, bga heat sink figure 18. 5v to 1v derating curve, bga heat sink a pplica t ions i n f or m a t ion load current (a) power loss (w) 4 5 4620a f13 3 2 0 2 3 5 6 8 9 10 1 7 6 12v to 1v power loss curve 5v to 1v power loss curve 12 13 15 16 17 19 20 22 23 24 26 load current (a) power loss (w) 4 5 6 4620a f12 3 2 0 1 7 12v to 2.5v power loss curve 5v to 2.5v power loss curve 2 3 65 8 9 10 12 13 15 16 17 19 20 22 23 24 26 ambient temperature (c) 0 load current (a) 18 20 22 120 4620a f15 16 14 0 10 40 80 100 20 60 12 8 6 4 2 26 24 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 18 20 22 4620a f16 16 14 0 10 40 80 100 120 20 60 12 8 6 4 2 26 24 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 18 20 22 4620a f17 16 14 0 10 40 80 100 120 20 60 12 8 6 4 2 26 24 400lfm 200lfm 0lfm figure 14. 5v power loss curve ambient temperature (c) 0 ch1 and ch2 combined load current (a) 18 20 22 4620a f18 16 14 0 10 40 80 100 120 20 60 12 8 6 4 2 26 24 400lfm 200lfm 0lfm load current (a) power loss (w) 4 5 6 4620a f14 3 2 0 1 8 7 3 5 6 8 9 10 12 13 15 16 17 19 20 22 23 24 26 12v to 5v power loss curve
ltm4620a 28 4620af for more information www.linear.com/4620a figure 19. 12v to 2.5v derating curve, no heat sink figure 20. 5v to 2.5v derating curve, no heat sink figure 21. 12v to 2.5v derating curve, with heat sink figure 22. 5v to 2.5v derating curve, with heat sink a pplica t ions i n f or m a t ion ambient temperature (c) 0 load current (a) 4620a f19 0 25 40 80 100 140120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 4620a f20 0 25 40 80 100 140120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 4620a f21 0 25 40 80 100 140120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 4620a f22 0 25 40 80 100 140120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 4620a f23 0 25 40 80 100 120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm ambient temperature (c) 0 load current (a) 4620a f24 0 25 40 80 100 120 20 60 20 15 10 5 30 400lfm 200lfm 0lfm figure 23. 12v to 5v derating curve, no heat sink figure 24. 12v to 5v derating curve, with heat sink
ltm4620a 29 4620af for more information www.linear.com/4620a a pplica t ions i n f or m a t ion layout checklist/example the high integration of ltm4620a makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout consid- erations are still necessary. ? use large pcb copper areas for high current paths, including v in , gnd, v out1 and v out2 . it helps to mini- mize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v in , pgnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track pin can be tied a common capacitor for regulator soft- start. ? bring out test points on the signal pins for monitoring. figure 25 gives a good example of the recommended layout. figure 25. recommended pcb layout gnd gnd gnd sgnd cntrl cntrl v out1 c out1 c out2 v out2 v in c in1 c in2 1 2 3 4 5 6 7 8 109 11 12 l k j h g f e d c b m a 4620a f25
ltm4620a 30 4620af for more information www.linear.com/4620a figure 26. typical 5v in to 16v in , 1.5v and 1.2v outputs a pplica t ions i n f or m a t ion 4620a f26 ltm4620a v in temp run1 run2 track1 track2 f set c out2 470f 6.3v 2 c out4 470f 6.3v 2 r fb2 ** 60.4k r2 10k c out1 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc sgnd gnd track1 track2 diffp diffn diffout r fb1 ** 40.2k pgood2 v out2 1.2v at 13a c ff ** 220pf c bot ** 100pf c comp ** c out3 100f 6.3v r4 121k r1* 10k d1* 5.1v zener 5v to 16v intermediate bus c5 0.1f c9 0.1f c1 22f 25v c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f v out1 1.5v 13a r3 10k intv cc + *pull-up resistor and zener are optional **see table 5 + + c in (opt) intv cc v in r7 100k
ltm4620a 31 4620af for more information www.linear.com/4620a typical a pplica t ions figure 27. ltm4620a 2-phase, 5v at 20a design with temperature monitoring 4620a f27 ltm4620a v in temp run1 run2 track1 track1 track2 f set c out2 220f 10v r5 8.25k r2 5k c out1 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 pgood1 mode_pllin clkout intv cc extv cc pgood1 pgood1 5v intv cc sgnd gnd diffp diffn diffout c out4 220f 10v c out3 100f 6.3v r1* 10k d1* 5.1v zener 7v to 16v intermediate bus c9 0.1f c1 22f 25v c2 22f 25v c11 22f 25v c3 22f 25v c10 4.7f + + * pull-up resistor and zener are optional intv cc intv cc intv cc ltc2997 a/d c 1.8v 4mv/k 470pf 0.1f v cc gnd v ref v ptat d + d ? v out 5v 26a v in
ltm4620a 32 4620af for more information www.linear.com/4620a t ypical a pplica t ions figure 28. ltm4620a 3.3v and 2.5v output tracking 4620a f28 ltm4620a v in temp run1 run2 track1 track2 f set c out2 100f 6.3v r8 19.1k r2 10k c out1 100f 6.3v phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 mode_pllin clkout intv cc extv cc pgood1 pgood1 intv cc intv cc intv cc intv cc sgnd gnd diffp diffn diffout r5 13.3k pgood2 r9 60.4k r1* 10k d1* 5.1v zener 5v to 16v intermediate bus c5 0.1f c1 22f 25v r7 90.9k c2 22f 25v c3 22f 25v c4 22f 25v c10 4.7f + + r3 10k * pull-up resistor and zener are optional 33pf v out1 3.3v v in v out1 3.3v 13a v out2 2.5v 13a 100pf c out4 220f 6.3v c out3 100f 6.3v r6 100k
ltm4620a 33 4620af for more information www.linear.com/4620a t ypical applica t ions figure 29. 4-phase, 3.3v at 50a, 750khz 4620a f29 ltm4620a v in temp run1 run2 track1 track2 f set r5 13.3k r2 5k c out1 100f 6.3v 2 phasmd v out1 v outs1 sw1 v fb1 v fb v fb2 comp1 comp comp2 v outs2 v out2 sw2 pgood2 pgood1 mode_pllin clkout clk1 clk1 intv cc extv cc pgood1 pgood1 sgnd gnd diffp diffn diffout r1* 10k d1* 5.1v zener 5v to 16v intermediate bus c1 22f 25v c20 0.22f c2 22f 25v c3 22f 25v c10 4.7f ltm4620a v in temp run1 run2 track1 track2 f set phasmd v out1 v outs1 sw1 v fb1 v fb2 comp1 comp2 v outs2 v out2 sw2 pgood2 pgood2 comp mode_pllin clkout intv cc extv cc pgood1 pgood2 sgnd gnd diffp diffn diffout 7v to 16v intermediate bus 5k c5 22f 25v c15 22f 25v c12 22f 25v c16 4.7f intv cc intv cc1 intv cc2 intv cc1 intv cc2 * pull-up resistor and zener are optional 220pf c out4 100f 6.3v 2 c out3 100f 6.3v 2 c out2 100f 6.3v 2 v out 3.3v 50a v in r6 100k r9 100k v fb
ltm4620a 34 4620af for more information www.linear.com/4620a ltm4620a component lga pinout p ackage descrip t ion pin id function pin id function pin id function pin id function pin id function pin id function a1 v out1 b1 v out1 c1 v out1 d1 gnd e1 gnd f1 gnd a2 v out1 b2 v out1 c2 v out1 d2 gnd e2 gnd f2 gnd a3 v out1 b3 v out1 c3 v out1 d3 gnd e3 gnd f3 gnd a4 v out1 b4 v out1 c4 v out1 d4 gnd e4 gnd f4 mode_pllin a5 v out1 b5 v out1 c5 v out1s d5 v fb1 e5 track1 f5 run1 a6 gnd b6 gnd c6 f set d6 sgnd e6 comp1 f6 sgnd a7 gnd b7 gnd c7 sgnd d7 v fb2 e7 comp2 f7 sgnd a8 v out2 b8 v out2 c8 v out2s d8 track2 e8 diffp f8 diffout a9 v out2 b9 v out2 c9 v out2 d9 gnd e9 diffn f9 run2 a10 v out2 b10 v out2 c10 v out2 d10 gnd e10 gnd f10 gnd a11 v out2 b11 v out2 c11 v out2 d11 gnd e11 gnd f11 gnd a12 v out2 b12 v out2 c12 v out2 d12 gnd e12 gnd f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 gnd k1 gnd l1 gnd m1 gnd g2 sw1 h2 gnd j2 v in k2 v in l2 v in m2 v in g3 gnd h3 gnd j3 v in k3 v in l3 v in m3 v in g4 phasemd h4 gnd j4 v in k4 v in l4 v in m4 v in g5 clkout h5 gnd j5 gnd k5 gnd l5 v in m5 v in g6 sgnd h6 gnd j6 temp k6 gnd l6 v in m6 v in g7 sgnd h7 gnd j7 extv cc k7 gnd l7 v in m7 v in g8 pgood2 h8 intv cc j8 gnd k8 gnd l8 v in m8 v in g9 pgood1 h9 gnd j9 v in k9 v in l9 v in m9 v in g10 gnd h10 gnd j10 v in k10 v in l10 v in m10 v in g11 sw2 h11 gnd j11 v in k11 v in l11 v in m11 v in g12 gnd h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd package row and column labeling m ay vary among module products. review each package layout carefully.
ltm4620a 35 4620af for more information www.linear.com/4620a information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion lga package 144-lead (15mm 15mm 4.41mm) (reference ltc dwg # 05-08-1844 rev b) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pad 1 corner detail a package bottom view 3 pads see notes suggested pcb layout top view 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 ltmxxxxxx module dia 0.630 pad 1 3x, c (0.22 x45) detail a 0.630 0.025 sq. 143x s yxeee l k j h g f e d c b m a 12345678 10 9 1112 lga package 144-lead (15mm 15mm 4.41mm) (reference ltc dwg # 05-08-1844 rev b) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 144 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature lga 144 0312 rev b tray pin 1 bevel package in tray loading orientation component pin ?a1? symbol a b d e e f g h1 h2 aaa bbb eee min 4.31 0.60 0.36 3.95 nom 4.41 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 max 4.51 0.66 0.46 4.05 0.15 0.10 0.05 notes dimensions total number of lga pads: 144 x y aaa z aaa z e d detail b bbb z detail b substrate mold cap z h2 h1 a b e g e f b
ltm4620a 36 4620af for more information www.linear.com/4620a linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2013 lt 0113 ? printed in usa r ela t e d p ar t s p ackage p ho t o part number description comments LTM4628 dual 8a, single 16a module regulator pin compatible with ltm4620a; 4.5v v in 26.5v, 0.6v v out 5.5v, 15mm 15mm 4.32mm ltm4627 15a module regulator 4.5v v in 20v, 0.6v v out 5.5v, 15mm 15mm 4.32mm ltm4611 ultralow v in , 15a module regulator 1.5v v in 5.5v, 0.8v v out 5v, 15mm 15mm 4.32mm ltm4620 dual 13a or single 26a lower output voltage range, 0.6v to 2.5v, pin compatible design r esources subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation t ools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging.

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